Various techniques for enhancing semiconductor device performance through manipulation of carrier mobility have been investigated in the semiconductor industry. One of the key elements in this class of technology is the manipulation of stress in the channel of transistor devices by employing lattice mismatched materials in source/drain regions. Such lattice mismatched materials may be advantageously employed to generate stress on a semiconductor device, for example, by applying biaxial stress or uniaxial stress in a channel of a metal-oxide-semiconductor field effect transistor (MOSFET) to improve performance, for example, by increasing an on-current.
The effect of uniaxial stress, i.e., a stress applied along one crystallographic orientation, on the performance of semiconductor devices, especially on the performance of a MOSFET (or a “FET” in short) device built on a silicon substrate, has been extensively studied in the semiconductor industry. For a p-type MOSFET (or a “PFET” in short) utilizing a silicon channel, the mobility of minority carriers in the channel (which are holes in this case) increases under uniaxial compressive stress along the direction of the channel, i.e., the direction of the movement of holes or the direction connecting the drain to the source. Conversely, for an n-type MOSFET (or an “NFET” in short) devices utilizing a silicon channel, the mobility of minority carriers in the channel (which are electrons in this case) increases under uniaxial tensile stress along the direction of the channel, i.e., the direction of the movement of electrons or the direction connecting the drain to the source. These opposite requirements for the type of stress for enhancing carrier mobility between the PFETs and NFETs have led to prior art methods for applying at least two different types of stress to the semiconductor devices on the same integrated chip.
Thompson et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices, Vol. 51, No. 11, pp. 1790-1797, November (2004) discloses a p-type filed effect transistor (PFET) employing embedded SiGe in source/drain (S/D) regions, which provide a compressive uniaxial stress along a channel between the embedded SiGe source/drain regions. The compressive uniaxial stress along the channel enhances mobility of holes, and as a consequence, increases the on-current of the PFET.
Ang et al., “Enhanced Performance in 50 nm N-MOSFETs with Silicon-Carbon Source/Drain Regions,” IEDM Technical Digest 2004, pp. 1069-1071, Digital Object Identifier: 10.1109/IEDM.2004.1419383, discloses an n-type filed effect transistor (NFET) employing embedded silicon-carbon (Si:C) in source/drain (S/D) regions, which provide a tensile uniaxial stress along a channel between the embedded silicon-carbon source/drain regions. The tensile uniaxial stress along the channel enhances mobility of electrons, and as a consequence, increases the on-current of the NFET.
In order to utilize the benefits of enhanced on-current from a PFET and an NFET, SiGe source/drain regions and silicon-carbon source/drain regions need to be formed on the same semiconductor substrate. However, the integration of both SiGe source/drain regions and silicon-carbon source/drain regions is challenging since SiGe source/drain regions need to be formed only for PFETs and silicon-carbon source/drain regions need to be formed only for NFETs.
In view of the above there exists a need for methods for forming hole mobility enhanced PFETs and electron mobility enhanced NFETs on the same semiconductor substrate.
Particularly, there exists a need for methods, i.e., an integration scheme, for forming SiGe source/drain regions and silicon-carbon source drain regions on the same semiconductor substrate.